The present invention generally relates to voltage-current conversion circuits, and more particularly to a voltage-current conversion circuit that realizes low distortion and low power consumption in the transconductance stage (or gm stage). The present invention also relates to an amplifier, mixer circuit, and mobile appliance, all of which utilize this voltage-current conversion circuit.
The digital terrestrial television broadcasting (ISDB-T) in Japan uses one segment (430 kHz) for mobile appliances. To make the function of receiving the digital terrestrial television broadcasting carried out by ICs (integrated circuits) and to incorporate the ICs into battery-driven mobile terminals, low power consumption, size reduction, immunity to interferences, and low distortion of the receiving tuner are important considerations.
In a low-IF (Intermediate Frequency) receiver system with a function of image rejection, the mixer circuit is one of the most important blocks. Conventionally, mixer circuits have a transconductance stage, that is, a voltage-current conversion circuit that amplifies input signal voltage V and converts it into current signal I, as shown in FIG. 10. When RF (Radio Frequency) input signals (RF,RFB) are inputted into transistors T1 and T2 (the voltage of a small signal between VBE1 and VBE2: Vin=Vin+−Vin−), currents Iout3 and Iout4 respectively represented by the following formulas (1) and (2) flow. It is noted that Iout3+Iout4=ISS.
                    [                  Mathematical          ⁢                                          ⁢          Formula          ⁢                                          ⁢          I                ]                                                                      I                      out            ⁢                                                  ⁢            3                          =                                                            I                SS                            ⁢              exp              ⁢                                                          ⁢                                                V                                      i                    ⁢                                                                                  ⁢                    n                                                                    V                  T                                                                    (                              1                +                                  exp                  ⁢                                                                          ⁢                                                            V                                              i                        ⁢                                                                                                  ⁢                        n                                                                                    V                      T                                                                                  )                                =                                    I              SS                                      (                              1                +                                  exp                  ⁢                                                                          ⁢                                                            -                                              V                                                  i                          ⁢                                                                                                          ⁢                          n                                                                                                            V                      T                                                                                  )                                                          (        1        )                                          I                      out            ⁢                                                  ⁢            4                          =                              I            SS                                (                          1              +                              exp                ⁢                                                                  ⁢                                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                                            V                    T                                                                        )                                              (        2        )            
According to this prior art, formulas (1) and (2) contain non-linear terms (exp), which means occurrence of distortion.
Also conventionally used is a voltage-current conversion circuit with cross-coupling as shown in FIG. 11. This voltage-current conversion circuit has first transistor T1 and second transistor T2 into which input signals (RF, RFB) are inputted from a base, third transistor T3 whose collector is connected to the emitter terminal of first transistor T1, and fourth transistor T4 whose collector is connected to the emitter terminal of second transistor T2. The bases of third and fourth transistors T3 and T4 are cross-coupled to each other's collectors. Resistor R7 is provided between the emitters of third and fourth transistors T3 and T4. In this voltage-current conversion circuit, when RF is inputted into transistors T1 and T2, currents Iout3 and Iout4 respectively represented by the following formulas (3) and (4) flow.
                    [                  Mathematical          ⁢                                          ⁢          Formulas          ⁢                                          ⁢          II                ]                                                                      I                      out            ⁢                                                  ⁢            3                          =                              I            SS                    -                                    V                              i                ⁢                                                                  ⁢                n                                                    R              7                                                          (        3        )                                          I                      out            ⁢                                                  ⁢            4                          =                              I            SS                    +                                    V                              i                ⁢                                                                  ⁢                n                                                    R              7                                                          (        4        )            
These formulas do not contain non-linear terms (exp), and therefore linearity improves. However, this circuit presents the problem of unstable operation upon input of high-frequency signals into first transistor T1 and second transistor T2 (the problem including unexpected oscillations with the base and collector in a common-mode with each other).
In the mixer circuit, there is a trade-off relationship between low distortion and low power consumption of the transconductance stage (or gm stage) (amplifier). To solve the above problem, non-patent document 1 discloses a technique of low distortion of a transconductor with cross-coupling, as shown in FIG. 12.
Referring to FIG. 12, transconductance stage (or gm stage) s100 has first transistor T1 and second transistor T2. Respective collectors are connected to respective power source terminals, and input signals (RF, RFB) are inputted into first and second transistors T1 and T2 from respective bases. Transconductance stage (or gm stage) s100 also has third transistor T3 whose collector is connected to the emitter terminal of first transistor T1, and fourth transistor T4 whose collector is connected to the emitter terminal of second transistor T2. The bases of third and fourth transistors T3 and T4 are cross-coupled to each other's collectors. Transconductance stage (or gm stage) s100 further has fifth transistor T5 that shares the base and emitter with third transistor T3 and acquires a current signal from the collector, and sixth transistor T6 that shares the base and emitter with fourth transistor T4 and acquires a current signal from the collector. Third transistor T3 and fifth transistor T5 (fourth transistor T4 and sixth transistor T6) constitute a current mirror. The current mirror ratio here is 1:1. Resistor R7 is provided between the emitters of fifth and sixth transistors T5 and T6 (T3 and T4), emitter terminals 1 and 2 of these transistors are respectively provided with constant current sources Iin1 and Iin2.
Transconductance stage (or gm stage) s100 amplifies input signal voltage Vin and converts it into a current signal.
In transconductance stage (or gm stage) s100 shown, since the currents that flow through transistors T1 and T3 (T2 and T4) are equal, the following formulas (5) and (6) are obtained.
[Mathematical Formula III]VBE1+VBE4=VBE2+VBE3  (5)VBE1=VBE3, VBE2=VBE4  (6)
When RF is inputted into transistors T1 and T2 (the voltage of a small signal between VBE1 and VBE2:Vin=Vin+−Vin−), RF signal Vin is directly fed into resistor R7, so that a signal current represented by formula (7) flows across resistor R7.
                    [                  Mathematical          ⁢                                          ⁢          Formula          ⁢                                          ⁢          IV                ]                                                                      i                      R            7                          =                              υ                          i              ⁢                                                          ⁢              n                                            R            7                                              (        7        )            
Currents Iout3 and Iout4 are respectively represented by formulas (8) and (9).
                    [                  Mathematical          ⁢                                          ⁢          Formula          ⁢                                          ⁢          V                ]                                                                      I                      out            ⁢                                                  ⁢            3                          =                              1            2                    ⁢                      (                                          I                SS                            -                                                υ                                      i                    ⁢                                                                                  ⁢                    n                                                                    R                  7                                                      )                                              (        8        )                                          I                      out            ⁢                                                  ⁢            4                          =                              1            2                    ⁢                      (                                          I                SS                            +                                                υ                                      i                    ⁢                                                                                  ⁢                    n                                                                    R                  7                                                      )                                              (        9        )            
These do not contain non-linear terms (e.g., ln and exp) similar to the conventional principles as (3),(4), and current mirror structures based on conventional cross-coupled principle, provide for low distortion operation. Transconductances gm 3 and gm 4 are as represented by formula (10) obtained by differentiating formulas (8) and (9).
                    [                  Formula          ⁢                                          ⁢          VI                ]                                                                      gm          ⁢                                          ⁢          3                =                              gm            ⁢                                                  ⁢            4                    =                      1                          2              ⁢                              R                7                                                                        (        10        )            
As an example of a conventional IQ mixer, patent document 1 and non-patent document 2 propose a quadrature mixer as shown in FIG. 13.
In this figure, the transconductance stage (or gm stage) will be referred to as Gm, and the SW (switch) stage of I or Q as SW_I or SW_Q. High-frequency signal RF and its inversed signal will be respectively referred to as RF and RFB, local signal and its inverse signal respectively as LO_I (LO_Q) and LO_IB (LO_QB), and intermediate-frequency signal IF (intermediate frequency) and its inversed signal respectively as IF_I (IF_Q) and IF_IB (IF_QB).
Referring to FIG. 13, quadrature mixer q100 has: I switching portion SW_I that generates, from the first signal (RF, RFB) and the second signal (LO_I, LO_IB), a third signal (IF_I, IF_IB) as the product; and Q switching portion SW_Q that generates, from the first signal (RF, RFB) and the fourth signal (LO_Q, LO_QB), a fifth signal (IF_Q, IF_QB) as the product. Transconductance stage (or gm stage) Gm, which amplifies the first signal (RF, RFB) and inputs the amplified signal into switching portions SW_I and SW_Q as a current signal, is common.
The operation of mixer circuit q100 will be described referring to FIG. 13. I mixer (Gm−SW_I) and Q mixer (Gm−SW_Q) multiply high-frequency signal RF, which is a received signal, respectively by local signal LO_I and local signal LO_Q and carry out frequency conversion. As the multiplication results, the mixers respectively generate intermediate-frequency signal IF_I and intermediate-frequency signal IF_Q.
By making input transconductance stage (or gm stage) Gm common, not only the number of elements are decreased, but there is a possibility of a decrease in power by half, low distortion, and low noise, compared with two independent Gilbert cell mixers.
Further, with the quadrature mixer, when the local signal has a sine wave or triangular wave, a point of intersection of quadrature signals I, IB, Q, and QB appears at π/2 intervals, even though IQ balance of the local signals are not good, as shown in FIG. 14(b). Owing to this IQ mutual interference, output phase errors caused by local signals can be relaxed However, when input is in a square wave as shown in FIG. 14(a), the points of intersection become vague, making it impossible to amend output phase errors. Since the image rejection ratio (the ratio of the desired wave to the interfering wave) is determined by the output phase error and amplitude error of the mixer, in recent years the quadrature mixer has been referred to in literature of various types as an image rejection mixer with the function of amending phase errors.
Patent document 2 discloses a mixer circuit as shown in FIG. 15. Mixer circuit m100 has transconductance stage (or gm stage) Gm, switching portion SW that carries out frequency conversion, and current paths Ip1 and Ip2. Bypass currents Ip1 and Ip2 enable independent optimization of the operation currents of switching portion SW and transconductance stage (or gm stage) Gm.
Patent document 1: U.S. Pat. No. 6,029,059
Patent document 2: Japanese Patent Publication No. 4-129407
Non-patent document 1: Hidehiko Aoki “Introduction to Functional Circuit Design of ICs” CQ Publishing, 1992.
Non-patent document 2: Jackson Harvey and Ramesh Harjani “Analysis and Design of an Integrated Quadrature Mixer with Improved Noise Gain and Image Rejection” IEEE International Symposium Circuits and Systems vol. IV pp. 786-789 May 2001.
However, the structure of the transconductance stage (or gm stage) shown in FIG. 12 has such a current relationship that Iout3:Iout5=Iout4:Iout6=1:1, and a current of approximately half Iin1 (Iin2) flows through Iout3 (Iout4). This restricts freedom of design; when reducing distortion and improving gain by increasing the currents for transistors T5 and T6, which are central to differential amplification operation, the circuit configuration requires an approximately twice as much current as the currents that flow through optimized transistors T5 and T6. Thus, power consumption cannot be prevented from increasing.